TLDR
- Cadence announced ChipStack’s Level 5 autonomy at Computex 2026 for AI-driven chip design workflows automation.
- The system uses NVIDIA Nemotron models and OpenShell runtime to support governed autonomous engineering execution.
- Cadence says ChipStack can reduce five-week verification loops to less than one day in deployments.
- NVIDIA engineers are expected to use ChipStack agents with Xcelium simulation and Jasper verification tools.
- Cadence expanded its AI portfolio after acquiring ChipStack and launching new agentic design products recently.
Cadence has announced what it describes as the industry’s first fully autonomous virtual agentic AI design engineer for semiconductor development.
The new capability extends the ChipStack AI Super Agent to Level-5 autonomy, allowing it to execute complex chip design and verification workflows with limited human direction.
The system is built on Cadence’s AI-driven electronic design automation portfolio, NVIDIA Nemotron models, and NVIDIA OpenShell runtime security.
Cadence said the technology is intended to help engineering teams shorten verification cycles while keeping engineers able to inspect, guide, and collaborate with the autonomous system.
ChipStack Moves to Level-5 Autonomy
Cadence introduced the expanded ChipStack AI Super Agent at Computex 2026, positioning it as a virtual engineer for chip design and verification. The system is designed to handle tasks such as specification review, RTL generation, verification planning, simulation, formal analysis, debug, and design convergence.
The company said the AI agent can evaluate intermediate results, choose next steps, and continue iterating toward closure across engineering workflows. This approach shifts engineers toward reviewing outcomes and setting direction instead of manually guiding every step.
Cadence said NVIDIA engineers are expected to use ChipStack agents with Cadence Xcelium Logic Simulation and Jasper Formal Verification. The company said these workflows can deliver more than 40X faster RTL validation cycles and reduce a typical five-week verification loop to less than one day.
NVIDIA Models and OpenShell Support Deployment
The ChipStack AI Super Agent uses NVIDIA Nemotron models to support autonomous reasoning across design and verification activity. Cadence said the system remains connected to its physics-based design and verification engines, which provide computational models and signoff-accurate results.
The agent runs inside NVIDIA OpenShell, a sandboxed runtime environment for autonomous agents. OpenShell is designed to enforce governance through policy controls, isolation, and managed access to tools, infrastructure, and design data.
NVIDIA executive Timothy Costa said the combination of ChipStack, OpenShell, and Nemotron models gives customers a faster and more secure path for developing advanced semiconductors. Cadence said the security framework is intended to support production use while protecting sensitive intellectual property.
Cadence Expands Agentic AI Design Portfolio
Cadence’s announcement follows its acquisition of ChipStack in November 2025 and the launch of its first product in February 2026. The company later expanded its AI super-agent portfolio at CadenceLIVE in April.
The portfolio now includes ViraStack AI Super Agent for custom and analog design, InnoStack AI Super Agent for digital implementation and signoff, and Cadence AgentStack for workflow orchestration. ChipStack now adds full autonomy to that wider product set.
Paul Cunningham, senior vice president and general manager of Cadence’s System Verification Group, said customers are using AI to support more ambitious silicon designs with greater speed and confidence. He said ChipStack moves Cadence from AI assistance toward autonomous virtual engineering inside secure and governed environments.
The launch reflects growing use of AI agents in semiconductor engineering, where design complexity and validation workloads continue to increase. Cadence said the ChipStack AI Super Agent is intended to automate real design and verification work while keeping engineering teams connected to progress and decisions.
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